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g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 1 - features : description : * 65,536 words by 16 bits organization. * fast access time and cycle time. * dual cas input. * low power dissipation. * read-modify-write, ras -only refresh, cas -before- ras refresh, hidden refresh and test mode capability. * 256 refresh cycles per 4ms. * available in 40-pin 400 mil soj ,and 40/44 pin tsop (ii). * single 5.0v 10% power supply. * all inputs and outputs are ttl compatible. * fast page mode operation. the glt41116 is a 65,536 x 16 bit high- performance cmos dynamic random access memory. the glt41116 offers fast page mode ,and has both byte write and word write access cycles via two cas pins. the glt41116 has symmetric address and accepts 256-cycle refresh in 4ms interval. all inputs are ttl compatible. fast page mode operation allows random access up to 256x16 bits, within a page, with cycle times as short as 18ns. the glt41116 is best suited for graphics, and dsp applications requiring high performance memories. high performance 30 35 40 45 max. ras access time, ( t rac ) 30 ns 35 ns 40 ns 45 ns max. column address access time, ( t aa ) 15 ns 18 ns 20 ns 22 ns min. fast page mode cycle time, ( t pc ) 18 ns 21 ns 23 ns 25 ns min. read/write cycle time, ( t rc ) 65 ns 70 ns 75 ns 80 ns max. cas access time ( t cac ) 10 ns 11 ns 12 ns 12 ns
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 2 - pin configuration : pin descriptions: name function a 0 - a 7 address inputs ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/lower byte control we write enable oe output enable dq 0 - dq 15 data inputs / outputs v cc +5v power supply v ss ground nc no connection glt41116 soj top view tsop(type ii) top view
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 3 - absolute maximum ratings* capacitance* t a =25 c, v cc =5v 10%, v ss =0v operating temperature, t a (ambient) .......................................-0 c to +70 c storage temperature(plastic)....-55 c to +150 c voltage relative to v ss . ..............-1.0v to + 7.0v short circuit output current......................50ma power dissipation ......................................1.0w symbol c in1 c in2 c ou t par ameter address input ras , lcas , ucas , we , oe data input/output max. 5 7 7 unit pf pf pf *note: operation above absolute maximum ratings can adversely affect device reliability. *note: capacitance is sampled and not 100% tested electrical specifications l cas means ucas and lcas . l all voltages are referenced to gnd. l after power up, wait more than 100 m s and then, execute eight cas -before- ras or ras -only refresh cycles as dummy cycles to initialize internal circuit. block diagram :
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 4 - truth table: glt41116 function ras casl cash we oe address dqs notes standby h h ? x h ? x x x high-z read: word l l l h l row/col data out read: lower byte l l h h l row/col lower byte,data- out upper byte,high-z read: upper byte l h l h l row/col lower byte,high-z upper byte,data- out write: word(early write) l l l l x row/col data-in write: lower byte (early) l l h l x row/col lower byte,data-in upper byte,high-z write: upper byte (early) l h l l x row/col lower byte,high-z upper byte,data-in read write l l l h ? l l ? h row/col data- out,data-in 1,2 fast-page- mode read 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l h h l l row/col col data-out data-out 1 1 fast-page- mode write 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l l l x x row/col col data-in data-in 2 2 fast-page- mode read- write 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l h ? l h ? l l ? h l ? h row/col col data- out,data-in data- out,data-in 1,2 1,2 hidden refresh read write l ? h ? l l ? h ? l l l l l h l l x row/col row/col data-out data-in 1 2,3 ras -only refresh l h h x x row high-z cbr refresh h ? l l l x x high-z 4 notes: 1. these read cycles may also be byte read cycles (either ucas or lcas active). 2. these write cycles may also be byte read cycles (either ucas or lcas active). 3. early write only. 4. at least one of the two cas signals must be active ( ucas or lcas ).
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 5 - dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc =5v 10%, v ss =0v, unless otherwise specified. sym. parameter test conditions access time min. typ max. unit notes i li input leakage current (any input pin) 0v v in 5.5v (all other pins not under test=0v) -10 +10 m a i lo output leakage current (for high-z state) 0v v out 5.5v output is disabled ( hiz) -10 +10 m a i cc1 operating current, random read/write t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1,2 i cc2 standby current,(ttl) ras , ucas , lcas at v ih other inputs 3 v ss 4 ma i cc3 refresh current, ras-only ras cycling, ucas , lcas at v ih t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 2 i cc4 operating current, edo page mode ras at v il , ucas , lcas address cycling: t pc = t pc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1,2 i cc5 refresh current, cas before ras ras , ucas , lcas address cycling: t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1 i cc6 standby current, (cmos) ras 3 v cc -0.2v, ucas 3 v cc -0.2v, lcas 3 v cc -0.2v, all other inputs 3 v ss 2 ma v il input low voltage -1 +0.8 v 3 v ih input high voltage 2.4 v cc +1 v 3 v ol output low voltage i ol = 4.2ma 0.4 v v oh output high voltage i oh = -5ma 2.4 v notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc( max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions specified i cc( max.) is measured with a maximum of one transition per address cycle in random read/write and fast page mode. 3. specified v il( min.) is steady state operation. during transitions v il( min.) may undershoot to -1.0v for a period not to exceed 20ns. all ac parameters are measured with v il( min.) 3 v ss and v ih(max.) v cc .
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 6 - ac characteristics (0 c t a 70 c, see note 1,2) test condition :v cc =5.0v 10%, v ih /v il =2.4v/0.8v,v oh /v ol =2.4v/0.4v parameter t rac = 30 ns t rac = 35 ns t rac = 40 ns t rac = 45 ns symbo min. man. min. max. min. max. min. max. unit notes read/write cycle time t rc 65 - 70 - 75 - 80 - ns read midify write cycle time t rwc 80 - 99 - 105 - 110 - ns access time from ras t rac - 30 - 35 - 40 - 45 ns 3,4 access time from cas t cac - 10 - 11 - 12 - 12 ns 3,4 access time from column address t aa - 15 - 18 - 20 - 22 ns 3,4 cas to output in low-z t clz 0 - 0 - 0 - 0 - ns 3 output buffer turn-off delay from cas t off 3 8 3 8 3 8 3 8 ns 7 transition time(rise and fall) t t 3 50 3 50 3 50 3 50 ns 2 ras precharge time t rp 25 - 25 - 25 - 25 - ns ras pulse width t ras 30 100k 35 100k 40 100k 45 100k ns ras hold time t rsh 10 - 12 - 12 - 13 - ns cas hold time t csh 30 - 36 - 40 - 46 - ns cas pulse width t cas 10 10k 12 10k 12 10k 13 10k ns ras to cas delay time t rcd 13 20 17 24 18 28 18 33 ns 4 ras to column address delay time t rad 10 15 12 17 13 20 13 23 ns 4 cas to ras precharge time t crp 5 - 5 - 5 - 5 - ns 8 row address setup time t asr 0 - 0 - 0 - 0 - ns row address hold time t rah 7 - 7 - 8 - 8 - ns column address setup time t asc 0 - 0 - 0 - 0 - ns column address hold time t cah 6 - 6 - 6 - 6 - ns column address hold time referenced to ras t ar 26 - 30 - 34 - 39 - ns column address lead time referenced to ras t ral 15 - 18 - 20 - 23 - ns read command setup time t rcs 0 - 0 - 0 - 0 - ns read command hold time referenced to ras t rrh 0 - 0 - 0 - 0 - ns 9 read command hold time referenced to cas t rch 0 - 0 - 0 - 0 - ns 9 we hold time referenced to cas t wch 6 - 6 - 6 - 6 - ns 10 write command hold time referenced to ras t wcr 26 - 30 - 34 - 39 - ns 5 we pulse width t wp 6 - 6 - 6 - 6 - ns 10
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 7 - parameter t rac = 30 ns t rac = 35 ns t rac = 40 ns t rac = 45 ns symbo l min. max. min. max. min. max. min. max. unit notes we lead time referenced to ras t rwl 10 - 11 - 12 - 12 - ns we lead time referenced to cas t cwl 10 - 11 - 12 - 12 - ns data-in setup time t ds 0 - 0 - 0 - 0 - ns 11 data-in hold time t dh 7 - 7 - 8 - 8 - ns 11 data hold time referenced to ras t dhr 27 - 31 - 36 - 41 - ns 6 we setup time t wcs 0 - 0 - 0 - 0 - ns 5 ras to we delay time t rwd 47 - 58 - 63 - 68 - ns 5 cas to we delay time t cwd 24 - 29 - 30 - 30 - ns 5 column address to we delay time t awd 29 - 36 - 38 - 40 - ns 5 cas setup time( cas before ras refresh) t csr 5 - 5 - 5 - 5 - ns cas hold time( cas before ras refresh) t chr 10 - 10 - 10 - 10 - ns ras to cas precharge time t rpc 5 - 5 - 5 - 5 - ns cas precharge time(cbr counter test cycle) t cpt 20 - 20 - 20 - 20 - ns access time from cas precharge t cpa - 18 - 21 - 23 - 25 ns 3 fast page mode read/write cycle time t pc 18 - 21 - 23 - 25 - ns fast page mode read modify write cycle time t prwc 48 - 60 - 63 - 65 - ns cas precharge time(fast page mode) t cp 5.5 - 6 - 7 - 7 - ns ras pulse width(fast page mode) t rasp 30 100k 35 100k 40 100k 45 100k ns ras hold time from cas precharge t rhcp 25 - 25 - 25 - 30 - ns access time from oe t oea - 10 - 11 - 12 - 12 ns oe to delay time t oed 8 - 8 - 8 - 8 - ns output buffer turn-off delay time from oe t oez 3 8 3 8 3 8 3 8 ns 7 oe hold time t oeh 6 - 6 - 7 - 7 - ns we hold time(hidden refresh cycle) t whr 15 - 15 - 15 - 15 ns refresh time(256cycles) t ref - 4 - 4 - 4 - 4 ms
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 8 - notes 1. an initial pause of 100 m s is required after power-up followed by any 8 ras only refresh or cas before ras refresh cycles to initialize the internal circuit. 2. v ih( min.) and v il(min.) are reference levels for measuring timing of input signals. transition times are measured between v ih(min.) and v il(max.) , ac measurements assume t t = 3ns. 3 . measured with an equivalent to 2 ttl loads and 100pf. 4. for read cycles, the access time is defined as follows: input conditions access time t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rad (max.) < t rad and t rcd t rcd (max.) t aa (max .) t rcd (max.) < t rcd t cac (max.) t rad (max.) and t rcd (max.) indicate the points which the access time changes and are not the limits of operation. 5. t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the data sheet as electric characteristics only. if t wcs 3 t wcs ( min.) , the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd ( min.) , t rwd 3 t rwd (min.) and t awd 3 t awd (min.) , then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. 6. t ar , t wcr , and t dhr are referenced to t rad (max.) . 7. t off (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to v oh or v ol . 8. t crp (min) requirement should be applicable for ras , cas cycle preceded by any cycles. 9. either t rch ( min.) or t rrh (min.) must be satisfied for a read cycle. 10. t wp (min.) is applicable for late write cycle or read modify write cycle. in early write cycles, t wch ( min.) should be satisfied. 11. this specification is referenced to cas falling edge in early write cycles and to we falling edge in late write or read modify write cycles.
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 9 - read cycle
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 10 - early write cycle note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 11 - late write cycle ( oe controlled write) note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 12 - read - modify - write cycle
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 13 - fast page read cycle note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 14 - fast page early write cycle note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 15 - fast page read-modify-write cycle note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 16 - cas before ras refresh cycle ras-only refresh cycle
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 17 - hidden refresh cycle ( read )
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 18 - hidden refresh cycle ( write ) note : d out = open
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 19 - cas -before- ras counter test cycle read cycle write cycle read-modify-write
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 20 - ordering information part number speed power feature package GLT41116-30J4 30ns normal fpm soj 400mil 40l glt41116-35j4 35ns normal fpm soj 400mil 40l glt41116-40j4 40ns normal fpm soj 400mil 40l glt41116-45j4 45ns normal fpm soj 400mil 40l glt41116-30tc 30ns normal fpm tsop 400mil 44l glt41116-35tc 35ns normal fpm tsop 400mil 44l glt41116-40tc 40ns normal fpm tsop 400mil 44l glt41116-45tc 45ns normal fpm tsop 400mil 44l parts numbers (top mark) definition : glt 4 11 16 - 40 j4 note : c cdrom , h hdd. example : 1.glt710008-15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016-40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : mix voltage config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 21 - package information 400mil 40 pin small outline j-form package (soj)
g-link glt41116 64k x 16 cmos dynamic ram with fast page mode may 1998 (rev 2) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 22 - 40/44 lead thin small outline package tsop(type ii)

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